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DM93L28 Dual 8-Bit Shift Register
March 1989 Revised August 1999
DM93L28 Dual 8-Bit Shift Register
General Description
The DM93L28 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers. The multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources; 2) the clock of each register may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input.
Features
s 2-input multiplexer provided at data input of each register s Gated clock input circuitry s Both true and complementary outputs provided from last bit of each register s Asynchronous master reset common to both registers
Ordering Code:
Order Number DM93L28N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
VCC = Pin 16
GND = Pin 8
Pin Descriptions
Pin Names S D0, D1 CP Data Inputs Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) MR Q7 Q7 Master Reset Input (Active LOW) Last Stage Output Complementary Output Description Data Select Input
(c) 1999 Fairchild Semiconductor Corporation
DS010200
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DM93L28
Functional Description
The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7). The clocking of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a number of gates. The clock OR gate drives the eight clock inputs of the flip-flops in parallel. When the two clock inputs (the separate and the common) to the OR gate are LOW, the slave latches are steady, but data can enter the master latches via the R and S input. During the first LOW-toHIGH transition of either, or both simultaneously, of the two clock inputs, the data inputs (R and S) are inhibited so that a later change in input data will not affect the master; then the now trapped information in the master is transferred to the slave. When the transfer is complete, both the master and the slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last remaining HIGH clock input, the transfer path from master to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new data can enter the master. Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal. Each 8-bit shift register has a 2-input multiplexer in front of the serial data input. The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression: Serial data in: SD = SD0 + SD1 An asynchronous master reset is provided which, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal. Shift Select Table Inputs S L L H H D0 L H X X D1 X X L H Output Q7 (tn+8) L H L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial n+8 = Indicates state after eight clock pulse
Logic Diagram
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DM93L28
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) tw(L) Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Clock Pulse Width HIGH or LOW MR Pulse Width with CP HIGH MR Pulse Width with CP LOW 0 30 30 0 0 55 55 60 70 Parameter Min 4.5 2 0.7 -400 4.8 +7 Nom 5 Max 5.5 Units V V V A mA C ns ns ns ns ns
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max, VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V MR, Dx CP (7, 10) S CP Com IIL LOW Level Input Current VCC = Max, VI = 0.3V MR, Dx CP (7, 10) S CP Com IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 2) VCC = Max -2.5 Conditions VCC = Min, II = -10 mA 2.4 0.3 1 20 30 40 60 -400 -600 -800 -1200 -25 25.3 mA mA A A Min Max -1.5 Units V V V mA
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
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DM93L28
Switching Characteristics
VCC = +5.0V, TA = +25C Symbol fMAX tPLH tPHL tPHL Parameter Maximum Shift Right Frequency Propagation Delay CP to Q7 or Q7 Propagation Delay MR to Q7 CL = 15 pF Min 5.0 45 80 110 Max Units MHz ns ns
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DM93L28 Dual 8-Bit Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16EUnits
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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